Senior Design Verification Engineer

Roles and Responsibilities

• Develop testbenches using UVM methodology for SoC verification.
  
• Create test cases based on functional requirements and write code to verify them.
  
• Collaborate with cross-functional teams to identify and resolve issues during verification process.
  
• Utilize SystemVerilog, Ethernet, DDR protocols knowledge to develop comprehensive verification plans.
  
• Participate in peer reviews to ensure high-quality deliverables.