Senior ASIC/RTL Engineer (5-10 yrs)

Position Vacant : "ASIC RTL"

Location : Bangalore

Work Mode : WFO

No of days working : 5days

Experience : 5-10 years

Availability : Immediate to 30 days joiners

Company Description :

Welcome to Semi Leaf consulting Service! Semi Leaf consulting firm is a team of experts that help to find candidates with specialized skills in industries such as Semiconductor/VLSI/EDA & Embedded domains.

Role Description :

This is a full-time opportunity for "ASIC RTL" with SEMI LEAF located in Bengaluru. The candidate will be responsible for day-to-day tasks associated with present role with our clients.

Key Responsibility :

- Understand RTL at structural level, IP boundaries, IP parameters

- Understand IP design

- Add assertions where needed

- Generate various constraints necessary for the IP

- RTL build flow setup and maintenance

- Do the quality checks of the IP like Lint/CDC/RDC/Synth/Timing checks/waiver creation across milestones

- Participate in IP integration to the subsystem level

- Write sample test bench to verify the basic functionality of the IP/block

- Do the first level of triage of the functional issues reported

- Understand the reports out of quality checks such as Lint/CDC/RDC/Synth/Timing checks and suggest fixes in the RTL

- Work with a functional verification team to meet coverage and quality standards.

- Guarantee quality/timely deliverables meeting project's schedule.

- Help to improve/automate the design process.

Preferred Experience :

- Knowledge of ASIC development flows

- Knowledge of front-end RTL design tools and methodologies.

- Knowledge of system Verilog

- Multi-clock domain designs.

- Design constraints for synthesis and static timing analysis.

- Experience in rtl linting tools, reset domain crossings, clock domain crossings, synthesis, RAM generation (area, timing, power)

- Knowledge of AXI/AMBA protocol

- Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, dfx, power.

a. Verification - coverage, test plan, debug

b. Physical design - timing, clock crossings, reset crossings, ECOs (manual, formal)

c. Ability to work and effectively collaborate with partners

- Knowledge of scripting languages- like- Perl, TCL or shell

- Experience with DMAs, PCIe, ordering, datapath virtualization, performance, flow control a plus.