Analog Layout Engineer

Role & responsibilities

• Design and optimize complex layouts for mixed signal and analog circuits in deep sub-micron CMOS technologies
• Collaborate with circuit designers to floor plan and complete layouts, ensuring seamless integration and optimal performance
• Run physical design/reliability verification, debug and fix violations, ensuring the highest quality and reliability of our AMS IP's
• Review and analyze layouts with circuit designers, providing expert feedback and guidance to ensure optimal design
• Contribute to layout integration and final verification for tape out, ensuring a smooth and successful project delivery

Required Skills

• 3-11 years of experience as an IC Layout Designer with analog/mixed signal layout experience. (Synopsys Or Cadence or Siemens).
• Proven experience with layout techniques for device matching, noise isolation, electro-migration, power distribution, latch-up and ESD circuits using state of the art nanometer process technologies
• Proficiency with Cadence Virtuoso XL layout tool and Mentor Calibre physical design verification tools (DRC, LVS, ERC) or equivalent
• Experience debugging and resolve LVS/DRC/ERC errors independently
• Exposure to TSMC FinFET process technology and its constraints for analog layout techniques and qualities
• Experience with Place and Route tools and scripting languages (perl, TCL, Python, or Cadence Skill)
• Experience with memory layout.
• Bachelors degree in electrical engineering, or relevant technical field, or equivalent practical experience.

Perks and benefits

As per company norms