Analog Layout Engineer

Job Description for Layout Design Engineer:

1. B.Tech or M.Tech. in Electronics and Electrical Engineering from an institute of repute.
2. 4+ to 8 years of experience in Analog and SERDES IP Layout Design.
3. The candidate should have relevant experience in following Analog IPs, blocks and SERDES IPs i.e. DLL, PLL, Clocking path Analysis, SERDES System Design and Analysis, Power Delivery Analysis, Transmitter (With or without equalization FFE), Receiver (with equalization CTLE, DFE), Channel Analysis, LDO, RCOMP, Sensors – Process Monitor, Temp Sensor, Voltage Sensor, GPIOs, High Speed View / Test IOs, DFX, High Speed ADC etc.
4. The candidate should have worked on any of the Analog IP layout mentioned above or block that are part of one of the following SERDES protocols i.e. DDR IO, UCIe, PCIe, HBIO, MIPI – CDPHY, HDMI etc.
5. The candidate must have knowledge of LEF development and power rails/distribution design in the layout.
6. The candidate should be well versed with DFY (Yield), EMIR, ESD and High Voltage requirements and fixes.
7. The candidate should be well versed with the design tools like Cadence Virtuoso, DRC/LVS analysis tools e.g. ICV, Calibre and Reliability Analysis tools etc.
8. Expertise in any scripting language (e.g. PERL, TCL, Python, SKILL) will be also be preferred.
9. The candidate necessarily should have very good communication skills and should be a team player.
10. The candidate should be having problem solving approach and should be able to report blocking issues during the project, as required.