Technical Manager

Hands on experience in test case preparation and execution

Should be able to lead a team of DV engineers.

• IP/Subsystem/SOC verification experience.
• Expertise in HVL and HDL (System Verilog, Verilog).
• Advanced knowledge of HVL methodology (UVM).
• Solid verification skills in problem solving, constrained random testing, and debugging.
• Solid understanding of reusable verification framework.
• Knowledge on PCI Express/DDR/USB will be a huge plus .
• Experience with System Verilog Assertion (SVA).
• Experience writing scripts in languages such as Perl or Python a plus .
• Programming experience in C/C++ and assembly a plus .
• Experience defining coverage space and writing coverage model a plus .
• Experience with GLS and Low Power Verification is a plus .
• Should be a great teammate with excellent communication skills and the desire to take on diverse challenges.
• Experience with formal verification tool (Jasper Gold or others) is not required but will be a huge plus .