RTL Technical Manager

Quest Global is an organization at the forefront of innovation and one of the world\u00E2\u20AC\u2122s fastest growing engineering services firms with deep domain knowledge and recognized expertise in the top OEMs across seven industries. We are a twenty-five-year-old company on a journey to becoming a centenary one, driven by aspiration, hunger and humility.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible, possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.

As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we\u00E2\u20AC\u2122re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:
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Roles & Responsibilities:

• Understanding the RTL design and Uarch of IPs and integrating them in sub-systems
• \u00C2SoC IP Uarch definition and RTL development\u00C2
• \u00C2Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc.
• \u00C2Design for Testability (DFT) checks
• \u00C2Low Power Checks
• \u00C2RTL Synthesis and STA support
• \u00C2Pre and Post Silicon functional verification support\u00C2
• \u00C2Close collaboration with different domain teams
• \u00C2\u00C2 DDR knowledge

Required Skills (Technical Competency):

• Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 15+ years of IP/SoC Design Experience
• \u00C2Experience is SoC design and integration for complex SoCs is a must.
• \u00C2Experience in Synthesis / Understanding of timing concepts is a plus.
• \u00C2Should have knowledge of AMBA protocols - AXI, AHB, APB besides SoC clocking/reset architecture.
• \u00C2Strong RTL design and coding experience in Verilog, system Verilog, VHDL etc.
• \u00C2Experience with micro-architecture and design of digital IPs and subsystems.

Desired Skills:

• Knowledge of PCIe/CXL and DDR4/5 interfaces and related controller design is a strong plus.

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