Sr. Silicon Design Engineer (AECG ASCI RTL Design / Integration)

• As part of the AECG ASIC/Custom silicon team, you will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.
• We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

THE PERSON:

• As a SOC RTL Integration Engineer/Lead, you will work with chip architects to conceive design, help with architecture/product definition through early involvement in the product life-cycle.

KEY RESPONSIBILITIES:

• Work with chip architect to understand architecture concept and high level requirements
• Convert chip spec to RTL using internal and external IPs
• Plan and deliver RTL for continuous integration testing
• Support the verification team to devise appropriate test plans and verification strategy
• Experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies.
• Earlier experience with SoC Integration , Processor based architectures needed.
• Self-driven and capable for independent work and independent decision making.
• Knowledge in frontend design experience on IPs involve processor based sub-system, Serial Standard interfaces, Memory controllers
• Exposure to Low-power design, System Security considered as added advantage
• Hands on front-end design of complex multi clock domain blocks
• Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog.
• Experience in Spyglass for lint and CDC checks.
• Experience in synthesis and LEC flow.
• Experience in identifying and implementing complex ECO in netlist.
• Defining and debugging timing constraints.
• Knowledge on Verification Methodologies to actively participate in Debug Analysis.
• Knowledge about system level flows and interaction with Firmware and Software would be added advantage.

PREFERRED EXPERIENCE:

• Experience in leading complex subsystem or SOC level integration, quality cleanup and delivery to DV, physical design teams
• Strong understanding of SOC globals like clocking, reset, boot and power management flows, low power design techniques, security
• Expertise with quality checks like CDC, Lint, VCLP, LEC
• Strong technical engineer who communicates we'll with great collaboration skills

ACADEMIC CREDENTIALS:

• Candidate must have a bachelors degree in Electronics/Electrical Engineering and 5+ years of experience in relevant areas.