Physical Verification Engineer (Sr. Silicon Design Engineer)

We are looking for an adaptive, self-motivative Physical Verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market.

THE PERSON:

As the SoC Physical Verification Engineer, you will be responsible for the end-to-end physical verification of complex System-on-Chip (SoC) designs, ensuring compliance with industry standards and design rules. You will oversee verification flows and work closely with the layout, design, and DFM (Design for Manufacturing) teams to guarantee that all design constraints are met before tape-out. This role requires expertise in verification tools, deep knowledge of design rule checking (DRC), layout versus schematic (LVS) checks, and a strong commitment to quality and reliability in advanced technology nodes.

KEY RESPONSIBILITIES:

• Lead the SoC physical verification including DRC, LVS, antenna checks, and electrical rule checking (ERC), ensuring all layout requirements meet foundry specifications and project timelines.
• Develop, enhance, and maintain verification flows using tools such as Mentor Graphics Calibre, Synopsys IC Validator. Streamline and automate flows to improve efficiency and accuracy
• Work closely with the design and block level teams to resolve DRC and LVS violations. Proactively identify potential design issues, provide guidance on best practices, and ensure full compliance with foundry design rules.
• Interface with cross-functional teams, including IP, physical design, and packaging, to ensure that physical verification issues are resolved in alignment with project specifications.
• Mentor junior engineers in physical verification, best practices, and troubleshooting techniques. Provide training on physical verification tools and methodologies as needed.

PREFERRED EXPERIENCE:

• Proficiency with physical verification tools such as Mentor Calibre, Synopsys IC Validator, or Cadence Pegasus.
• Strong knowledge of DRC, LVS, ERC, and antenna rules, as well as other physical verification checks.
• Experience in debugging complex DRC and LVS violations and collaborating on design fixes.
• Familiarity with scripting languages such as Tcl, Perl, or Python to automate verification tasks and improve workflow efficiency.
• Understanding of design for manufacturing (DFM) requirements and techniques
• Excellent problem-solving abilities, attention to detail, and a collaborative attitude

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering