Quest Global Hiring Physical Design Engineer

• 3+ years of professional experience in physical design, preferably with high performance designs.
• Experience in minimum one of the Full Chip Chip Integration activities such as Full Chip Floor Planning, Power Planning , Bus Planning, Full Chip timing, Full Chip Reliability and Full Chip Physical Verification is desirable.
• Experience in FEC,VCLP.
• Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
• Experience in developing PD metrics dashboard scripts for QOR tracking is a plus
• Experience in modifying STA constraints to check timing closure feasibility
• Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm

Please forward your updated profile to below details to chakradhar.marupuru@quest-global.com.