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Marvell Semiconductors

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3.9

based on 68 Reviews

40 Marvell Semiconductors Jobs

Physical Design Engineer

Marvell India Pvt Ltd

3.9

based on 68 Reviews

5-10 years

Bangalore / Bengaluru

1 vacancy

Physical Design Engineer

Marvell Semiconductors

posted 11hr ago

Job Role Insights

Flexible timing

Key skills for the job

Computer Networking Front End Automotive Engineering Semiconductor Basic Intellectual Property

+ 4 more

Job Description

Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.
You will be responsible for maintaining, enhancing, and supporting Marvells Place and Route Flow, leveraging industry-standard EDA tools.
Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues.
Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

What Were Looking For

MTech with 5+ years of block level Physical design experience, Or BTech with 6+ years of experience.
Good understanding of ASIC physical design block level flow covering all stages like synthesis, floorplanning, PNR , signoff STA, PV etc.. with complex clocking structure.
Ability to work with block front end engineers and full chip designers to analyse and explore physical implementation options to achieve better routability and timing QOR for complex designs.
Good understanding of STA, Physical verification at block level.
Experience in scripting and flow development.
Very good hands on experience in Cadence Innovus, Synopsys Primtime, Calibre tools.
Flexibility to work with multiple teams across different sites.
Candidates that are able to join quickly would be highly preferred .

Employment Type: Full Time, Permanent

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