Physical Design Engineer

An exciting opportunity is awaiting for you!


I am seeking PnR (PlaceAndRoute) Leads in the Physical Design field. If interested, kindly DM me or send your updated candidature to ratul.c@acldiital.com.


This role offers an Individual Contributor role as well as leadership opportunity to mentor juniors for our in house ODC and product partners.


Role Details: -
Job Location Bangalore
Experience: 6 to 12 years in Physical Design (PD) HandsOn
Notice Period: Immediate to 90 days


Technical Skills:

Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM) Well versed with the timing closure (STA), timing closure methodologies Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verification Experience in lower tech node (5nm) Good automation skills in PERL, TCL and EDA tool-specific scripting Able to take complete ownership for Block/sub-system for complete execution cycle Out of box thinking to meet tighter PPA requirements


Best Wishes
Ratul