STA/PNR/Synthesis - Lead

Job Opportunity: ASIC Physical Design Engineers (Multiple Roles)

We are hiring skilled ASIC Physical Design Engineers for exciting roles in PnR, Synthesis, STA, and Power/Physical Verification. If you have experience in advanced technology nodes, proficiency in EDA tools, and a passion for chip design, join our team in Bangalore.

Role & Responsibilities:

1. Physical Design Lead (PnR):
   
• Handle Full-Chip Physical Design, including floor planning, Place & Route (PnR), CTS, and Timing Closure.
• Resolve timing and congestion issues and ensure IR/EM checks and DRC/LVS sign-off.
• Work on lower technology nodes, preferably below 5nm, and multi-voltage designs.
• Develop automation scripts using Perl, Tcl, or EDA tool-specific languages.

1. Synthesis Lead:
   
• Perform Physical Synthesis using Fusion Compiler or Genus, debug flow issues, and optimize PPA.
• Analyze and debug using Conformal LEC and timing tools like PrimeTime or Tempus.
• Develop and debug SDC constraints and provide feedback to the design team.
• Automate processes with Tcl or Perl scripting.

1. STA Lead:
   
• Develop and validate timing constraints for pre and post-layout stages.
• Ensure timing closure through RC balancing, clock tree optimization, and abstraction techniques like Hyperscale or ILM.
• Perform RC scaling analysis for critical data paths and full-chip clock balancing.
• Collaborate with design teams for constraint integration and optimization.

1. Power and Physical Verification Lead:
   
• Design and analyze power grids, perform static and dynamic IR drop analysis, and optimize power.
• Execute Physical Verification checks (DRC, ERC, LVS, ANT, ESD) for low-power SoCs.
• Work on custom placement and routing tasks and automate workflows using scripting.

Preferred Candidate Profile:

• Experience: 4 to 10 years in ASIC Physical Design across roles like PnR, Synthesis, STA, or Power and Physical Verification.
• Expertise in advanced technology nodes, preferably below 5nm.
• Hands-on experience with tools like Cadence Innovus, Fusion Compiler, PrimeTime, Tempus, Redhawk, and Voltus.
• Proficiency in scripting languages such as Perl, Tcl, or EDA tool-specific scripts.
• Solid understanding of timing closure, IR/EM checks, and Physical Verification.

Perks and Benefits:

• Opportunity to work on cutting-edge designs in advanced technology nodes.
• Collaborative and innovative work environment.
• Professional growth with exposure to industry-leading tools and workflows.

Location: Bangalore
Joining Timeline: Immediate to 30 days

How to Apply:
If youre passionate about ASIC Physical Design and ready to take your career to the next level, send your resume to prabhu.p@acldigital.com or call 8754387484.