CPU RTL Power management Design Engineer

General Summary:

We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices.

In this role, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle.

As an RTL engineer you will own or participate in the following:

Performance exploration. Explore high performance strategies working with the CPU modeling team.

Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.

RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.

Functional verification support. Help the design verification team execute on the functional verification strategy.

Performance verification support. Help verify that the RTL design meets the performance goals.

Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.

Skillset looking for:

Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: Active power management (DVFS) , Idle power management , Limit management (TDP, Thermal and Over-current protection), Clock management, Debug and Trace architecture.

Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.

Knowledge of logic design principles along with timing and power implications.

Minimum Qualifications: