Senior Design Verification Engineer - UVM Verification Methodology (4-10 yrs)

Role : Senior Design Verification Engineer

Experience : 4 - 8 yrs

Job Description :

- Strong Familiarity with UVM Verification Methodology

- Knowledge of system-level architecture including buses like AXI/AHB/CHI/ACE5, bridges, memory controllers such as DDR3/DDR4/LPDDR3/LPDDR4, and peripherals such as USB and Ethernet

- Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim

- Demonstrate the ability to work with cross-functional teams

- Familiarity with processors and boot flow would be useful

- Familiarity with Software development flow including assembly and C is beneficial