Senior Engineer Verification

• Behavioral modeling: Verilog, Wreal or SV-RNM -Full
• AMS Verification for SoC or IPs -Full
• Test plan preparation as per the dynamics of product specifications - Full
• Dealing challenges with AMS methodologies of Cadence: irun\/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial
• Testcase Debug proposing new scenarios - Partial
• Handling project dynamics on scope, schedule and effort coming up with alternative verification plans, Mentoring Junior engineer Partial
• Ability to drive MSV project independently
• Drive enhancements in known methodologies

You are best equipped for this task if you have:

• Bachelors with 5+ years of experience
• Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage
• HDL\/HVL: Verilog\/Verilog-ams, SV\/UVM added advantage
• Tools: Cadence Xcelium + spectre\/ Synopsys XA-VCS\/ Mentor Eldo ADMS
• Automation: Perl\/python\/shell
• Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements
• Ability to drive projects and debug independently