Senior Staff Engineer Verification

• Be in continuous and intensive contact with our development sites worldwide
• Advise and support the experts from our business units in verification projects
• Drive the internal exchange of know-how and experience at Infineon
• Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineons design system and supporting their implementation in the development of new products
• Collaborate with other disciplines (eg Application Engineering) to define the verification methodology and the verification plan
• Design and develop the verification environment for ICs using the "Universal Verification Methodology" (UVM)
• Independently identify sub-modules that are particularly suitable for Formal Verification and apply this methodology
• Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach
• Use the Unified Power Format (UPF) to verify the low-power aspects of our designs

You are best equipped for this task if you have:

• You have a degree in Electrical Engineering, Computer Science or a similar academic discipline.
• You have at least five years of professional experience in Metric Driven Verification (digital & mixed-signal) and Formal Verification.
• You have experience with microcontroller-based ICs and ideally with security and safety requirements.
• You are experienced in the creation and dissemination of methods in the area of functional verification.
• You have an excellent understanding of and application skills in UVM and UPF.
• You have sound knowledge of firmware and RTL design (VHDL) - experience with Cadence verification software is a plus.
• You have some initial experience in technical leadership and project management.