Memory BIST -- Hardware verification Engineer

Responsibilities

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers.

Understand the design specification , Memory and Memory BIST engine connections

Develop the verification environment and test bench and creating testcases.

Debug fails using waveform, trace tools and debug RTL code

Develop skills in IBM Functional verification tools and methodologies.

Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design

Required education
Bachelor's Degree

Preferred education
Master's Degree

Required technical and professional expertise

5 + years of experience in Design Verification - demonstrated execution experience of verification of logic blocks

Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST

Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL)

Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl

Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow

Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails

Experience in verification coverage closure

Hardware debug skills backed by relevant experience on projects

Preferred technical and professional experience

Knowledge of Chip-Initialisation , SCAN , etc

Scripting Expertise backed up relevant experience in the same

Writing Verification test plans

Functional and code coverage analysis and debug