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High Speed IO Verification Engineer
2-6 years
Hyderabad / Secunderabad, Bangalore / Bengaluru
High Speed IO Verification Engineer
IBM
posted 10hr ago
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Flexible timing
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Job Description
The High Speed IO design team delivers both proprietary and industry standard interfaces for IBM's POWER systems' and Z Mainframe's processors. With a current data rate up to 64Gbps and rising, verifying the functionality of the digital and analog components in an efficient manner is necessary.
Your Role and Responsibilities
Job Duties:
A verification engineer should be able to create test plans and testbenches to verify both logic and microcode provided by logic designers. They should communicate with the logic designer to create and review a test plan document, and then implement a testcase from the document. Testcases are written in either cycle sim or event sim, depending on the application. Simulations should be randomized appropriately and executed in large numbers through batch submissions. Coverage should be collected and analyzed with the logic designer. Some amount of logic debug ability is expected.
About the Team:
The team in Austin, TX consists of analog circuit designers, logic designers, and verification engineers. We work with a global team to deliver IBM's proprietary high speed interfaces for its server processors.
Skills:
High-speed IO or Analog Mixed Signal Verification experience preferred, Testbench design, Automated testcase design (Fusion/C++), Sim coverage collection and analysis, Batch submission and queue management, Randomization management, General communication skills (written and on the phone)
Tools:
C/C++, SystemVerilog, UVM, Git, VHDL, AMS verification, Linux OS, KornShell & BASH scripting, NCSim, MESA Fusion, HDWB, AWAN, Mantis, PSL
Required Technical and Professional Expertise
Preferred Technical and Professional Expertise
Your Role and Responsibilities
Job Duties:
A verification engineer should be able to create test plans and testbenches to verify both logic and microcode provided by logic designers. They should communicate with the logic designer to create and review a test plan document, and then implement a testcase from the document. Testcases are written in either cycle sim or event sim, depending on the application. Simulations should be randomized appropriately and executed in large numbers through batch submissions. Coverage should be collected and analyzed with the logic designer. Some amount of logic debug ability is expected.
About the Team:
The team in Austin, TX consists of analog circuit designers, logic designers, and verification engineers. We work with a global team to deliver IBM's proprietary high speed interfaces for its server processors.
Skills:
High-speed IO or Analog Mixed Signal Verification experience preferred, Testbench design, Automated testcase design (Fusion/C++), Sim coverage collection and analysis, Batch submission and queue management, Randomization management, General communication skills (written and on the phone)
Tools:
C/C++, SystemVerilog, UVM, Git, VHDL, AMS verification, Linux OS, KornShell & BASH scripting, NCSim, MESA Fusion, HDWB, AWAN, Mantis, PSL
Required Technical and Professional Expertise
- Bachelors in Electrical Engineering
- Understanding of Analog circuits
- Project work with C/C++ and familiarity with Verilog/Vhdl, AMS verification
Preferred Technical and Professional Expertise
- Familiarity with IO SERDES design, Mixed Signal Analysis, and design verification
Employment Type: Full Time, Permanent
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What people at IBM are saying
Verification Engineer salary at IBM
reported by
6
employees
with 2-4
years exp.
₹5.5
L/yr - ₹16
L/yr
19%
more
than the average Verification Engineer Salary in India
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What IBM employees are saying about work life
based on 21.3k employees
Flexible timing
Monday to Friday
No travel
Day Shift
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