Senior Verification Engineer

Job Responsibilities

• Using advanced verification languages (HVL) and techniques to build a cutting-edge verification platform to fully evaluate memory designs at chip or block level on functionality
• Participating in creating full chip behaviour model that is distributed to Micron s world-wide external customer s months before silicon is available
• Building a verification plan, incorporating directed and random patterns that cover all features
• Understanding the functionality and timing requirements of the design
• Understand internal and external datasheets
• Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design

• 4+ years of experience in Verification
• Solid understanding of Verilog, System Verilog and object-oriented programming
• Experience in VIP development using UVM (or equivalent) is a must
• Good debugging and problem-solving skills are a must
• Experience defining coverage strategy and writing coverage model is a must
• Experience in simulator tools like Synopsys, Cadence, Mentor Graphics is preferred
• Experience in scripting language like Shell, Perl, Python is preferred
• Must possess good communication skills to convey complex technical concepts and ability to work well in a team
• Previous work experience in DRAM memory related fields is a plus