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Engaged Employer

Maven Wave Partners

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4.1

based on 105 Reviews

17 Maven Wave Partners Jobs

ASIC Verification Engineer

MAVEN WAVE PARTNERS (INDIA)PVT. LTD.

4.1

based on 105 Reviews

2-6 years

Bangalore / Bengaluru

1 vacancy

ASIC Verification Engineer

Maven Wave Partners

posted 19d ago

Job Role Insights

Flexible timing

Key skills for the job

C++ Basic CCTV Monitoring Digital Transformation ASIC Verification Process Simulation

+ 3 more

Job Description

Eviden, part of the Atos Group, with an annual revenue of circa 5 billion is a global leader in data-driven, trusted and sustainable digital transformation. As a next generation digital business with worldwide leading positions in digital, cloud, data, advanced computing and security, it brings deep expertise for all industries in more than 47 countries. By uniting unique high-end technologies across the full digital continuum with 53,000 world-class talents, Eviden expands the possibilities of data and technology, now and for generations to come.

Title: ASIC Verification Engineer

Location: Bangalore (Whitefield)

Experience: 3-5 years

Office Requirement: 3 Days WFO

Education: Bachelor s degree (B.E./B.Tech) or Master s degree (M.E./M.Tech)

Roles & Responsibilities:

Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team.
Write and perform the test plan in close cooperation with the logical design team.
Develop coverage models and verification environments using UVM-SystemVerilog / C++. Write, maintain and publish the verification specification.
Monitor, analyze and debug simulation errors.
Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.
Produce a maintainable and reusable code across projects

Required Skills and Experience

Curious, demanding and rigorous.
Mastering object oriented programming.
Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages
Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA)
Knowledge of simulation tools and coverage database visualization tools
Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints.

Our Offering:

Competitive salary package
Leave Policies: 10 Days of Public Holiday (Includes 2 days optional) & 22 days of Earned Leave (EL) & 11 days for sick or caregiving leave.
Benefit Plans (Insurance) - Medical & Life & Accidental & EDLI