Technical Lead: Physical Design

Dear Applicant

We, Cyient is hiring for Technical Leader: Physical Design for End to End Offshore-Onshore Model based Global Product R&D Solution Opportunity.

Base Location: Bangalore & Hyderabad

Experience Range: 10-20 Yrs

Pls Note: Based on Candidate Performance in End to End Full Chip Physical Design, Candidate might need to travel to Onshore.

Key Skills:

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes.

• Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2)
• Experience in Static Timing Analysis (PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).
  • Understanding the practical application of methodologies and Physical Design Tools, Flow Automation, and Improvements.
  • Experience in SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techniques.
• Excellent Customer interaction, Communication, Teamwork skills and managing a team of 10+
• Should have experience in handling >5M instance count , 1.5GHz frequency designs.
• Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.

• Interested Physical Design Leaders, kindly share updated CV to rajanikant.sharma@cyient.com for detailed discussion.

Thanks and Regards

Rajani Kant Sharma

Sr Recruiter: Global Lateral Hiring: Semicon Vertical

Cyient