Physical Design Lead

We are looking for an experienced Physical Design Lead with expertise in Netlist2GDSII implementation, including floor planning, power grid design, CTS, STA, and physical verification. The ideal candidate will have proficiency in Cadence and Synopsys tools and experience with 16nm and below technologies, along with a strong background in SoC integration and low-power/high-speed designs. Leadership in managing teams, handling complex designs, and proficiency in Tcl/Tk/Perl programming is essential, along with excellent communication and customer interaction.

Roles & Responsibilities:

• You should have 10+ years of hands-on experience with Netlist2GDSII implementation, including key processes such as floor planning, power grid design, placement, clock tree synthesis (CTS), routing, static timing analysis (STA), power integrity analysis, physical verification, and chip finishing.
• Expertise in physical design methodologies with experience working on sub-micron technologies (16nm and below).
• Proficiency with PnR tools from Cadence and Synopsys (Innovus, ICC2).
• Strong background in Static Timing Analysis (PrimeTime SI), EM/IR drop analysis (PT-PX, Redhawk), and physical verification (Calibre).
• Practical knowledge in applying methodologies and physical design tools, with experience in flow automation and process improvements.
• Hands-on experience in SoC integration, low-power and high-speed designs, and advanced physical verification techniques.
• Demonstrated ability to manage and lead a team of 10+ members.
• Proven success in handling designs with >5M instance count and 1.5GHz frequency.
• Expertise in programming (Tcl/Tk/Perl) to automate design processes and improve efficiency.
• Excellent customer interaction, communication, and teamwork skills, ensuring smooth collaboration with internal teams and clients.