ASIC Lead Designer (Global Product R&D from Scratch)

Dear Applicant

We, Cyient is hiring for multiple new positions in Lead Designer: End to End ASIC Design Flow for End to End Offshore-Onshore model based Global Product R&D Solution from scratch.

Exp Range: 18-30 Yrs
Base Location: Bangalore, Hyderabad

Key Skills:

Looking for an experienced senior design engineer with 18+ years of experience in ASIC/SOC/IP/block level design and functional verification using system verilog/UVM.

Good knowledge ASIC flow

Hands on experience in RTL Integration, coding, Synthesis, CDC and LEC
The ideal candidate will have strong command of UVM, advanced UVM and system Verilog
Key responsibilities:

Work with the customer team on the RTL Integration and coding, CDC, Synthesis and DFT tasks.

Work closely with Architects and come up the SoC design and support the other team members and also support verification and Synthesis team

Need to more proactive in driving both onsite and offshore team ~10 to 20 members

Guide the team technically and help to co-ordinate with customer team.

Possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB, ARM Cores etc....
Strong debugging skills to address Design issues quickly and collaboratly work with cross functional team
Take responsibility for Design closure and support verification team by addressing coverage and managing bug reports
proficiency in using industry standard EDA tools such as Questa, VCS or ModelSim
Experience with scripting languages like python, perl or TCL for automation tasks

Interested Applicants, Kindly share updated CV to rajanikant.sharma@cyient.com for detailed discussion.

Best Regards
Rajani Kant Sharma
Sr Recruiter: End to End Semicon Vertical
Cyient
Bangalore