Post Silicon Validation Lead

Dear Applicant,

We, Cyient is hiring for Post Silicon Validation Lead: Analog Peripherals/ PMIC: Bench Validation & Characterization (Offshore-Onshore Model based Global Product R&D from Scratch).

Experience Range: 10-20 Years
Base Location: Bangalore.

Key SKills:
1. As a lead, we are looking for specialized Leader in Advanced Analog: Bench Validation & Characterization.
2. Applicant must have strong experience in Project Planning and Execution from Scratch with Customer Interface Experience.
3. Will lead Bench Characterization for Analog IPs in SoC
4. Will lead the new team to successful and timely completion of bench characterization of analog IPs such as ADC, DAC, LDO, Thermal Sensor, CMPSS, Bandgap, Oscillator
5. Will be involved in Improving test flows, automations, test board, instrument usage optimization, team knowledge to achieve robust, efficient and optimal test setups
6. Will be involved in Planning for fastest Si-to-RTM cycle in next SoC
7. Must have worked on pre-Si SoC level validation of digital interfaces for analog IPs: ADC, DAC, CMPSS, TSENSE
8. Must have understanding of end-equipment and use-case of Resolver IP, working on demo setup for the same
9. Will be responsible for characterization of PLL, Thermal Sensor, OTP, GPIO, MTBF, PMB, RO, Oscillator, Filter, BBGEN
10. Must have understanding of VIL/VIH, VOL/VOH, Rise-time, Fall-time, Propagation-Delay, Jitter, Phase Noise, PSRR, Lock-Time etc.
11. Should have created automations using LabVIEW, VB, Python
12. Must have knowledge of block level design of analog IPs
13. Must have created setup for PLL, TSense, BBGEN, OTP
13. Must have trained new employees

Interested Applicants, Kindly share updated CV & availability slots to rajanikant.sharma@cyient.com for detailed discussion.

Best Regards
Rajani Kant Sharma
Sr Recruiter: Semiconductor Vertical
Cyient