Staff Engineer: Analog-Mixed Signal IC Design

Dear Applicants

We, Cyient is hiring for Staff Engineer: Analog-Mixed Signal IC Design for End to End Offshore-Onshore Model based Global Product R&D from scratch-based Opportunity.

Base Location: Bangalore & Hyderabad

Experience Range: 5-12 Yrs

Key Skills:

• The candidate should have experience in Analog and Mixed Signal Design with focus on PMIC blocks such as DC-DC converter (BUCK,BOOST), LDOs  and clocking circuits. Strong fundamentals of CMOS design, and active filter design. The various task involves, circuit design, validation, mixed signal validation, and reliability validation.
  Exposure to PMIC designs High speed digital circuit design and analysis with timing and flow closure. Digitally assisted analog circuit and techniques. The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of PLL. Good knowledge of control systems, Bandgap reference, bias, op-amps, feedback and compensation techniques.
• You  will be joining an expanding analog/mixed-signal circuit design team involved in design and development on cutting-edge foundry process development nodes.
• Your responsibilities will include but not be limited to:
• The candidate should have experience in Analog and Mixed Signal
• Design with focus on Analog blocks and clocking circuits. Strong fundamentals of CMOS design, passive RC circuits, switched cap circuits are a must for this role
• The various task involves, circuit design, validation, mixed signal validation, and reliability validation.
• High speed digital circuit design and analysis with timing and flow closure. Digitally assisted analog circuit and techniques.
• The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of PLL. Good knowledge of control systems, band gaps, bias, op-amps, LDOs, feedback and compensation techniques. Experience in LC VCO/DCO design.
• Good exposure to performance parameters of VCO as well as complete PLL architecture.

Interested ASIC Verification SME's, kindly share updated CV to rajanikant.sharma@cyient.com for detailed discussion.

Thanks and Regards

Rajani Kant Sharma

Sr Recruiter: Global Lateral Hiring: Semicon Vertical

Cyient