Design Verification Lead - System Verilog/UVM (10-15 yrs)

We are seeking an experienced Design Verification (DV) Lead to lead verification activities for complex designs. The ideal candidate will have expertise in System Verilog (SV), UVM (Universal Verification Methodology), and experience with industry-standard protocols.

The role involves managing verification tasks, mentoring a team of engineers, and ensuring robust and efficient verification processes.

Key Responsibilities :

- Develop and execute comprehensive verification plans for complex SoC/ASIC designs.

- Utilize System Verilog (SV) and UVM methodologies for functional verification.

- Drive testbench architecture, design, and implementation for various IPs or subsystems.

- Perform simulation-based verification, including test case development, coverage analysis, and debugging.

- Work on protocols such as PCIe, Ethernet, USB, or others to validate design implementations.

- Collaborate with cross-functional teams, including RTL designers and system architects, to ensure quality and completeness of design verification.

- Mentor and manage a team of verification engineers, ensuring timely and high-quality deliverables.

- Identify verification bottlenecks and propose process improvements.

- Track and report verification progress, ensuring adherence to project timelines.

Mandatory Skills :

SoC level - Static timing Analysis Engineer

Experience : 8+ years of relevant experience

Location : Bangalore

Expectations :

- Candidate should have strong STA fundamentals.

- Has done timing sign-off including timing margin calculations independently on SoC level.

- Experience in handling STA of multi-power domain designs.

- STA flow enhancement, abstraction with bottleneck identification.

- Proficient in design margins and SDC constructs.

- TAT reduction in multi-mode, multi power domain/designs.

- Generate timing ECOs for Physical design.-

- Drive ambitious schedules and enables dependent teams to accomplish.-

- Proficient with EDA tools from Synopsys/Cadence.-

- Excellent analytical & communication skills.-

- Show ability to collaborate in a multi-functional environment, cross-site or cross-time zone.-

- Proficient in Tcl and Perl or other scripting relevant language is a plus.

Skills to look for :

- SDC and constraints syntax

- Timing signoff tools like Primetime / Tempus is a must

- MMMC, DMSA or Tweaker

- Block /SOC,AOCV/POCV, TCL / Perl.

- 9+ years of experience in Design Verification with strong expertise in SystemVerilog and UVM.

- Proven experience in creating and executing verification plans.

- Strong debugging skills and experience with simulation tools like VCS, Questa, or Incisive.

- Knowledge of industry-standard protocols such as PCIe, Ethernet, USB, or similar.

- Hands-on experience in coverage-driven verification and achieving 100% functional coverage.

- Strong leadership skills with experience managing and mentoring a team of engineers.

- Excellent analytical and communication skills.

Nice to Have Skills :

- Experience with formal verification tools.

- Knowledge of scripting languages like Python, Perl, or Tcl for automation.

- Exposure to hardware-software co-verification or emulation platforms.

- Familiarity with low-power verification techniques and methodologies.

Education : Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Science, or a related field.

Benefits :

- Competitive salary and benefits package.

- Opportunity to work on cutting-edge verification projects.

- Professional growth and leadership development opportunities.

- Collaborative and innovative work environment.