Cadence Design Systems - RTL Principal Design Engineer - Static Timing Analysis (5-10 yrs)

Job Description :

We are seeking a highly skilled RTL Principal Design Engineer with a strong technical background in front-end design for high-performance SerDes IPs across various technology nodes (>100G rates).

The ideal candidate will have extensive experience in synthesis, timing closure, STA, and low-power implementation for cutting-edge Mixed-Signal Hybrid PHY IPs such as DDR, USB, PCIe, and Ethernet.

Key Responsibilities :

- Synthesize complex SerDes IPs across different process nodes, ensuring high performance and power efficiency.

- Execute Static Timing Analysis (STA) and timing closure for complex datapath designs and control FSMs operating at 2GHz and above in advanced technology nodes.

- Define and validate timing constraints, ensuring robust timing closure for high-speed critical paths in collaboration with backend teams.

- Implement low-power design techniques using CPF/UPF, optimizing for power efficiency in high-speed designs.

- Ensure design robustness through Lint, SDC, CDC, DFT, Low Power, and trial Place-and-Route (PnR) checks before handoff to backend teams or customers.

- Develop and verify structural DFT and at-speed ATPG methodologies to improve testability and yield.

- Work closely with Physical Design (PD) and Verification teams to ensure design convergence and seamless integration.

Required Skills & Experience :

- 10+ years of experience in front-end RTL design and synthesis for high-speed interfaces and SerDes IPs.

- Proficiency in Verilog/SystemVerilog, Synthesis tools (DC, Genus, or equivalent), and timing analysis tools (PT, Tempus, etc.

- Deep understanding of low-power design methodologies, power intent implementation using CPF/UPF, and power-aware synthesis.

- Strong expertise in DFT, ATPG, and structural testing techniques.

- Experience with industry-standard EDA tools for LINT, CDC, SDC validation, and low-power analysis.

- Ability to collaborate effectively with backend teams (PD, DFT, and STA) to achieve timing and power closure.

Preferred Qualifications :

- Experience in SerDes PHY, high-speed memory interfaces (DDR), and networking IPs.

- Familiarity with advanced technology nodes (7nm, 5nm, or below) and their design challenges.

- Strong debugging skills and ability to optimize designs for performance, area, and power