Staff Engineer - RTL Design

If you are passionate about pushing the boundaries of Design technology and thrive in a collaborative, dynamic environment, we invite you to join our team as a Design Engineer. Join usto be part of our journey in shaping the future of SoC design and innovation.

Responsibilities

• As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team integrating IP and developing logic for SoCs.
• You will work with the project team to understand and review the architecture, and develop the design specifications.
• Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks.
• You will work with the verification team to review test plans, and help debug design issues.
• You will work with the performance analysis team to evaluate and improve subsystem performance.
• You will also contribute to developing and enhancing the design methodologies used by the team.
• You will guide and support other members of the team as needed to enable the successful completion of project activities.
• You will balance other opportunities such as working with Project Management on activities, plans, and schedules

Required Skills and Experience:

• In addition to bringing your accomplishment of either Bachelors or Master s degree or equivalent experience in Computer Science or Electrical/Computer Engineering.

Experience of 8+ years working in design of complex compute subsystems or SoCs, you will need:

• Strong knowledge of digital hardware design and Verilog HDL!
• A thorough understanding and experience of the current design techniques for complex SoC development.
• Experience creating design specifications
• Experience developing RTL for SoC projects
• Experience with Perl, Python or other scripting language

Desired Skills and Experience:

• Experience with ARM-based designs and /or ARM System Architectures
• Experience integrating subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet
• Experience with SystemVerilog and verification methodologies UVM/OVM/e
• Experience leading small teams or projects

Experience or knowledge in the following areas

• Synthesis and timing analysis
• Static design checks, including CDC, RDC, X-Propagation, Linting
• Power management techniques
• DFT and physical implementation