DFT - PMTS Silicon Design Engineer

As a member of the AMD, you will help bring to life cutting-edge designs. As a member of the DFT team, you will work closely with the Architecture, IP design, Physical Design teams, and Product Engineers to achieve first pass silicon success.

THE PERSON:

The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• DFT Planning and Architecture definition
• Strong understanding on Scan Architecture and Scan features
• Scan insertion and ATPG pattern generation for Stuck at, Transition ATPG, IDDQ Pattern Generation
• GLS, Timing and Power Aware Simulations
• Test coverage and test cost reduction analysis
• Yield Analysis & Debug for Design root cause & Recovery
• Post Silicon Bring Up: Planning, Co-ordination, and Execution
• DFT Silicon bring up expertise from across tech various nodes
• Extensive Silicon Debug for Phasing closure and production enablement
• Experience of multiple SOC Tape-Outs and Post Silicon Bring-ups

PREFERRED EXPERIENCE:

• Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc)
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

ACADEMIC CREDENTIALS:

• Bachelor s or master s degree in Electronics/VLSI/Electrical Engineering