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Premium Employer

Advanced Micro Devices

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3.8

based on 249 Reviews

215 Advanced Micro Devices Jobs

MTS Silicon Design Engineer

Advanced Micro Devices, Inc

3.8

based on 249 Reviews

8-13 years

Hyderabad / Secunderabad

1 vacancy

MTS Silicon Design Engineer

Advanced Micro Devices

posted 6d ago

Job Role Insights

Flexible timing

Key skills for the job

Python Social Work Recruitment Gaming C++ Perl

+ 4 more

Job Description

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s CSoC DV, resulting in no bugs in the final design.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities:

Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and system-level verification
Specifying and owning design verification plan at SOC level/IP level
Specifying or reviewing verification plans for complex blocks within the ASIC
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :
o self-checking, reusable, automated verification environment : both at full-chip & block level
o Constrained random generators and reference models

Job Requirements and Skills:

Minimum 8+ years of experience in ASIC Design Verification
Must have excellent knowledge of ASIC Design Flow and SOC architecture
Experience in developing complex testbench/model in verilog, System verilog or SystemC
Experience with coverage-based verification methodology
Experience in writing testplans and testcases
Excellent debug skills in functional simulations are must.
Experience in random test generation, coverage analysis, failure debug
Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have
Strong Verilog, SystemVerilog, PLI interface, C/C++, Python/Perl/shell scripts programming skills.
Must have good communication skills and the ability/desire to foster a team environment.