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TSMC Physical Design Engineer Interview Questions and Answers

Updated 1 Oct 2024

TSMC Physical Design Engineer Interview Experiences

1 interview found

Interview experience
5
Excellent
Difficulty level
Hard
Process Duration
2-4 weeks
Result
-

I applied via Recruitment Consulltant and was interviewed in Sep 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. How can you solve noise/crosstalk
  • Ans. 

    Noise/crosstalk can be solved by proper floorplanning, routing, shielding, and using low noise components.

    • Proper floorplanning to minimize signal interference

    • Careful routing to reduce crosstalk between signals

    • Using shielding techniques to isolate noisy components

    • Utilizing low noise components in the design

    • Implementing signal integrity analysis to identify and mitigate noise issues

  • Answered by AI
  • Q2. Draw a simple timing setup and solution if violated
  • Ans. 

    Timing setup and solution for violation

    • Timing setup: input signal, clock signal, flip-flop

    • Solution for violation: adjust clock skew, optimize routing

    • Example: setup time violation due to long routing delay

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Be yourself and tell the truth

Interview questions from similar companies

I applied via Referral

Interview Questionnaire 

35 Questions

  • Q1. Tell me something about yourself
  • Ans. 

    I am a physical design engineer with experience in designing and optimizing integrated circuits.

    • I have a Bachelor's degree in Electrical Engineering

    • I have worked on multiple projects involving ASIC design and verification

    • I am proficient in using industry-standard EDA tools such as Cadence and Synopsys

    • I have experience in optimizing power, area, and timing constraints for ICs

    • I am a team player and have collaborated with...

  • Answered by AI
  • Q2. Can you explain more about your project, What was your role in it ?
  • Ans. 

    I worked on a project involving physical design of a microprocessor chip.

    • My role was to design and optimize the layout of the chip using industry-standard EDA tools.

    • I collaborated with the design team to ensure that the chip met performance and power requirements.

    • I also performed timing analysis and physical verification to ensure that the chip was manufacturable.

    • The project involved working with advanced process nodes...

  • Answered by AI
  • Q3. Which is the subject you like the most?
  • Ans. 

    I enjoy studying computer architecture and digital logic design.

    • Computer architecture

    • Digital logic design

    • Microprocessor design

    • VLSI design

  • Answered by AI
  • Q4. Can you draw a CMOS inverter and explain
  • Ans. 

    A CMOS inverter is a digital logic gate that converts a digital input signal to its complement.

    • It consists of a PMOS transistor and an NMOS transistor connected in series.

    • The input signal is connected to the gates of both transistors.

    • The output is taken from the drain of the PMOS transistor and the drain of the NMOS transistor.

    • When the input is high, the PMOS transistor is off and the NMOS transistor is on, resulting i...

  • Answered by AI
  • Q5. Can you explain 5 level of working of an Inverter
  • Ans. 

    An inverter has 5 levels of working: input, pre-driver, driver, output, and load.

    • Input stage receives the input signal and converts it to a digital signal.

    • Pre-driver stage amplifies the digital signal and sends it to the driver stage.

    • Driver stage amplifies the signal further and sends it to the output stage.

    • Output stage converts the amplified signal back to analog form.

    • Load stage receives the analog signal and drives t

  • Answered by AI
  • Q6. What is strong 1 and strong 0 concepts in an inverter
  • Ans. 

    Strong 1 and strong 0 are the maximum voltage levels that an inverter can output for logic 1 and logic 0 respectively.

    • Strong 1 is the maximum voltage level that an inverter can output for logic 1.

    • Strong 0 is the maximum voltage level that an inverter can output for logic 0.

    • These concepts are important in determining the noise margin of a digital circuit.

    • The noise margin is the difference between the minimum voltage lev...

  • Answered by AI
  • Q7. What you know about layout designing, which tool you have worked with
  • Ans. 

    Layout designing involves creating a physical representation of a circuit using CAD tools.

    • Layout designing is a crucial step in the physical design process of integrated circuits.

    • It involves placing and routing the components of a circuit to meet design specifications.

    • CAD tools commonly used for layout designing include Cadence Virtuoso, Synopsys IC Compiler, and Mentor Graphics Calibre.

    • Layout designers must consider f...

  • Answered by AI
  • Q8. Can you introduce yourself
  • Ans. 

    I am a Physical Design Engineer with experience in designing and optimizing integrated circuits.

    • I have a Bachelor's degree in Electrical Engineering

    • I have worked on projects involving ASIC design and verification

    • I am proficient in using tools such as Cadence and Synopsys

    • I have experience in optimizing power, area, and timing constraints

    • I am familiar with industry-standard design methodologies such as RTL-to-GDSII flow

  • Answered by AI
  • Q9. Which is your favorite subject throughout your course of study
  • Ans. 

    My favorite subject throughout my course of study is Digital Design.

    • I enjoyed learning about logic gates and how they can be used to create complex circuits.

    • I found the process of designing and testing digital circuits to be very satisfying.

    • I also appreciated the practical applications of digital design in fields like computer architecture and embedded systems.

    • I excelled in courses like Digital Logic Design and Compute...

  • Answered by AI
  • Q10. What is virtual ground concept in an op-amp
  • Ans. 

    Virtual ground is a concept where the non-inverting input of an op-amp is grounded to create a reference point for the inverting input.

    • Virtual ground is created by connecting the non-inverting input of an op-amp to ground.

    • This creates a reference point for the inverting input, which can be used to amplify the difference between the two inputs.

    • Virtual ground is commonly used in amplifier circuits and filters.

    • Examples of...

  • Answered by AI
  • Q11. Can a draw a basic transistor amplifier and explain
  • Ans. 

    A transistor amplifier is a circuit that uses a transistor to amplify the input signal.

    • A transistor amplifier consists of a transistor, a power supply, and input and output signals.

    • The transistor acts as a switch, controlling the flow of current through the circuit.

    • The input signal is applied to the base of the transistor, and the output signal is taken from the collector.

    • The gain of the amplifier is determined by the ...

  • Answered by AI
  • Q12. Why we prefer voltage divider bias circuit over others.
  • Ans. 

    Voltage divider bias circuit is preferred due to its stability and low sensitivity to temperature variations.

    • Provides stable bias voltage

    • Low sensitivity to temperature variations

    • Simple and easy to implement

    • Suitable for low power applications

    • Reduces noise and distortion

    • Examples: BJT amplifier circuits, op-amp circuits

  • Answered by AI
  • Q13. What is load line, What is difference between dc load line to that of ac load line
  • Ans. 

    Load line is a graphical representation of the relationship between voltage and current in a circuit.

    • DC load line represents the steady-state behavior of a circuit while AC load line represents the dynamic behavior of a circuit.

    • DC load line is a straight line while AC load line is a curved line.

    • DC load line is used to determine the operating point of a circuit while AC load line is used to analyze the small-signal beha...

  • Answered by AI
  • Q14. What is Q point, how does voltage divider bias fix Q point
  • Ans. 

    Q point is the operating point of a transistor. Voltage divider bias fixes Q point by setting the base voltage to a desired level.

    • Q point is the DC bias point of a transistor.

    • It is the point where the transistor operates in the active region.

    • Voltage divider bias sets the base voltage to a desired level, which in turn sets the Q point.

    • This ensures that the transistor operates in the desired region and provides the requi...

  • Answered by AI
  • Q15. What you know about stabilization concept in an amplifier
  • Ans. 

    Stabilization concept in an amplifier refers to the techniques used to prevent oscillations and ensure stable operation.

    • Stabilization is achieved by adding feedback components to the amplifier circuit

    • The feedback components can include resistors, capacitors, and inductors

    • Negative feedback is commonly used to stabilize amplifiers

    • Positive feedback can cause instability and oscillations

    • Stabilization techniques vary depend...

  • Answered by AI
  • Q16. Can draw n basic RC circuit for low pass filter and explain
  • Ans. 

    Yes, I can draw n basic RC circuits for low pass filter and explain.

    • An RC circuit consists of a resistor and a capacitor in series or parallel

    • The cutoff frequency of the low pass filter is determined by the values of R and C

    • The output voltage decreases as the frequency of the input signal increases

    • Examples of basic RC circuits include RC low pass filter, RC high pass filter, and RC bandpass filter

  • Answered by AI
  • Q17. How will be the charging and discharging of Capacitor in this circuit.
  • Ans. 

    The charging and discharging of capacitor in the circuit depends on the voltage and resistance of the circuit.

    • The capacitor charges when the voltage across it increases and discharges when the voltage decreases.

    • The rate of charging and discharging depends on the resistance of the circuit.

    • The time constant of the circuit determines the rate of charging and discharging.

    • The formula for time constant is T = R*C, where T is

  • Answered by AI
  • Q18. Can you draw the waveform for charging and discharging current.
  • Ans. 

    Yes, I can draw the waveform for charging and discharging current.

    • The waveform for charging current is a rising slope from zero to the maximum current value, followed by a plateau at the maximum value until the battery is fully charged.

    • The waveform for discharging current is a falling slope from the maximum current value to zero, followed by a plateau at zero until the battery is fully discharged.

    • The charging and disch...

  • Answered by AI
  • Q19. What are the conditions for an RC circuit to work as an integrator/differentiator Can you derive it with this circuit
  • Ans. 

    RC circuit works as integrator/differentiator under certain conditions. Can be derived with circuit analysis.

    • For an RC circuit to work as an integrator, the time constant (RC) should be large enough compared to the input signal frequency.

    • For an RC circuit to work as a differentiator, the time constant (RC) should be small enough compared to the input signal frequency.

    • The output voltage of an RC integrator circuit is pr...

  • Answered by AI
  • Q20. What is the difference between small signal analysis to that for large signal anaysis
  • Ans. 

    Small signal analysis is linear and deals with small variations around an operating point, while large signal analysis is nonlinear and deals with large variations.

    • Small signal analysis assumes that the circuit is linear and that the input signal is small enough to not affect the operating point of the circuit.

    • Large signal analysis deals with nonlinear circuits and assumes that the input signal is large enough to affec...

  • Answered by AI
  • Q21. How good are in programming. Rate out of 10
  • Ans. 

    I rate myself 8 out of 10 in programming.

    • I have experience in programming languages such as C++, Python, and Verilog.

    • I have developed scripts to automate tasks and improve efficiency.

    • I am constantly learning and improving my programming skills.

    • I have successfully completed several programming projects.

    • I am comfortable working with complex algorithms and data structures.

  • Answered by AI
  • Q22. What are second order effects in CMOS. Can you explain each one?
  • Ans. 

    Second order effects in CMOS and their explanation

    • Second order effects are non-linear effects that occur in CMOS devices

    • Some examples include channel length modulation, body effect, and drain-induced barrier lowering

    • Channel length modulation is the change in effective channel length due to the variation in drain-source voltage

    • Body effect is the change in threshold voltage due to the variation in substrate voltage

    • Drain-...

  • Answered by AI
  • Q23. How does the current equation changes when second order effects taken in account
  • Ans. 

    The current equation becomes more complex and includes additional terms when second order effects are considered.

    • Second order effects refer to non-linearities in the system that affect the current equation.

    • These effects can include things like parasitic capacitance, inductance, and resistance.

    • When second order effects are taken into account, the current equation may include additional terms such as higher order derivat...

  • Answered by AI
  • Q24. What you know about CMOS latch-up. Explain with help of circuitry.
  • Ans. 

    CMOS latch-up is a phenomenon where a parasitic thyristor is formed in a CMOS circuit, causing it to malfunction.

    • CMOS latch-up occurs when a parasitic thyristor is formed between the power supply and ground in a CMOS circuit.

    • This can happen when the voltage at the input or output pins exceeds the power supply voltage.

    • To prevent latch-up, designers use guard rings, substrate contacts, and other techniques to prevent the...

  • Answered by AI
  • Q25. How can we avoid latch up in a CMOS circuit
  • Ans. 

    Latch up in CMOS circuits can be avoided by implementing proper layout techniques and using guard rings.

    • Implement proper layout techniques

    • Use guard rings

    • Avoid asymmetric layout

    • Minimize substrate resistance

    • Use low-resistance substrate material

    • Avoid high substrate doping levels

    • Use ESD protection devices

    • Avoid high voltage gradients

    • Use proper power supply sequencing

  • Answered by AI
  • Q26. Why CMOS is preferred over NMOS and PMOS.
  • Ans. 

    CMOS is preferred over NMOS and PMOS due to its low power consumption, high noise immunity, and compatibility with digital circuits.

    • CMOS consumes less power than NMOS and PMOS.

    • CMOS has higher noise immunity due to complementary nature of transistors.

    • CMOS is compatible with digital circuits due to its ability to switch between high and low states.

    • NMOS and PMOS have higher power consumption and are not complementary in n...

  • Answered by AI
  • Q27. Draw cross sectional view an NMOS and explain its electrons flow level working
  • Ans. 

    An NMOS cross-sectional view and electron flow level working explanation.

    • NMOS stands for n-channel metal-oxide-semiconductor.

    • It is a type of MOSFET (metal-oxide-semiconductor field-effect transistor).

    • NMOS has a source, drain, and gate terminal.

    • When a voltage is applied to the gate, it creates an electric field that attracts electrons from the source to the drain.

    • The flow of electrons from source to drain is controlled ...

  • Answered by AI
  • Q28. Characteristics curve for NMOS, PMOS and CMOS
  • Ans. 

    Characteristics curve for NMOS, PMOS and CMOS are graphs that show the relationship between current and voltage.

    • NMOS curve shows that current increases with voltage until it reaches saturation

    • PMOS curve shows that current decreases with voltage until it reaches saturation

    • CMOS curve is a combination of NMOS and PMOS curves

    • CMOS curve shows that current flows only when both NMOS and PMOS are on

    • The threshold voltage is the

  • Answered by AI
  • Q29. Introduce yourself
  • Ans. 

    I am a Physical Design Engineer with experience in designing and optimizing integrated circuits.

    • I have a Bachelor's degree in Electrical Engineering

    • I have worked on multiple projects involving ASIC design and optimization

    • I am proficient in using EDA tools such as Cadence and Synopsys

    • I have experience in floorplanning, placement, and routing of digital circuits

    • I am familiar with industry-standard design methodologies su

  • Answered by AI
  • Q30. Why Intel?
  • Ans. 

    Intel is a leading technology company with a strong focus on innovation and cutting-edge products.

    • Intel has a reputation for being at the forefront of technological advancements

    • Intel invests heavily in research and development to create innovative products

    • Intel has a diverse range of products and services, providing opportunities for growth and development

    • Intel has a strong company culture that values collaboration, di

  • Answered by AI
  • Q31. What was the work in your previous company. Why you want to switch the company?
  • Ans. 

    I worked as a Physical Design Engineer in my previous company. I am looking for new challenges and opportunities to grow.

    • I was responsible for designing and implementing physical layouts of integrated circuits.

    • I collaborated with cross-functional teams to ensure timely delivery of projects.

    • I optimized designs for power, performance, and area.

    • I want to switch companies to gain exposure to new technologies and work on mo...

  • Answered by AI
  • Q32. One question to check how I deal with stress situations
  • Q33. One question to check how I Manage an Event Inside Intel
  • Q34. What is your salary expectation?
  • Ans. 

    I am open to discussing a salary that is commensurate with my experience and the responsibilities of the role.

    • I am flexible and open to negotiation

    • I am looking for a fair and competitive salary based on industry standards

    • I am willing to consider other benefits such as healthcare, retirement plans, and vacation time

    • I am interested in opportunities for growth and advancement within the company

  • Answered by AI
  • Q35. Any questions that you have to ask us?
  • Ans. 

    Yes, what are the biggest challenges your physical design team is currently facing?

    • Ask about the team's current projects and timelines

    • Inquire about any upcoming technology changes or advancements

    • Ask about the team's approach to problem-solving and collaboration

  • Answered by AI

Interview Preparation Tips

Round: Technical Interview
Experience: Basically they try know your technical knowledge through first, In fact this round is the more or less like an Elimination round where in you have to reply with little more explanation or until he moves to next question which mostly will be related to your answer. So jump into trouble by trying to make your own answer rather try to switch on to a topic that you well
Tips: A good grasp of Basic electronics and VLSI questions will help a lot in this round. Never go for an interview without brushing up your knowledge. Be prepared with self intro for atleast 2/3min such a way that any question from it can be answered with immense confidence level.

Round: Technical Interview
Experience: This was the round which I was able to perform well. I feel that the interviewer wanted to know more about my technical skills and hence more questions. A good preparation was required to tackle this round, and in fact I did. The interviewer was quite happy when I was able to give answer more than expected. NPTEL videos helped me a lot to face this round.
Tips: Be thorough with RC, RLC, circuit, its charging/discharging. Concept in transistor biasing, its fixing and stabilization have to known. Be ready with your subject of interest, and should be able to answer if asked from any corner of it.

Round: Technical Interview
Experience: As you can see, this round was more in VLSI stuffs. Since I said that I am not interested in programming, he changed the discussion into relevant domain. This round was more or less to check I fit into other positions also like Design Automation/Verification etc
Tips: Dont give an answer 'yes' for an area you dont know or rather you are not interested into
-> Take your own time to answer the question. Interviewer not more concerned about how fast you can answer.
-> I would suggestion you to watch this NPTEL video to learn about CMOS latch up. It helped me:-----?v=QlwcPjHpnH0

Round: HR Interview
Experience: More than a HR interview, it was more like an Behavioral round. The interview was taken by Skip level Manager. For last question, I asked 'what will be my actual work here and where can I find myself 2/3 years down the line?.
All the interviews where 1:1.

Tips: ->Never give answer 'no' for the last question I mentioned here
-> All the answers in this should be abide by ethics and values.
-> Know about the company and your work before hand.

Skill Tips: -> Be prepared well
-> Keep in mind that the Interviewer wont a preplanned set of questions to ask you and hence its all about how and what you answer. In fact, the whole Interview is just what you decide
-> Try to get rid of questions that you dont. Its better to say 'I dont know' rather than beating around the bush'
-> Be free out of Tension, take your own to answer, there is no harm in that.

Skills: Basic Digital Logic, Digital Design, Digital And Analogue Parts Of VLSI, VLSI, Basic Electronics, Analog And Digital Knowledge, Analog Integrated Circuits, CMOS Circuits, Analog Circuits
College Name: Government Model Engineering College, Thrikkakara

Skills evaluated in this interview

Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via LinkedIn and was interviewed in Jul 2023. There were 2 interview rounds.

Round 1 - Technical 

(4 Questions)

  • Q1. Floorplan strategies to calculate maximum macro counts that can be used in a block, placement constraints, congestion issues.
  • Ans. 

    Floorplan strategies involve calculating maximum macro counts, considering placement constraints and addressing congestion issues.

    • Floorplan strategies involve determining the maximum number of macros that can be accommodated within a block.

    • Placement constraints refer to the rules and guidelines that dictate where macros can be placed within the block.

    • Congestion issues arise when there is limited space or resources avai...

  • Answered by AI
  • Q2. Multi cycle paths, timing violations in reg2reg path.
  • Q3. Routing issues, signal integrity, IR drop analysis.
  • Q4. Logical DRC's, causes and fixing strategies.
Round 2 - Technical 

(3 Questions)

  • Q1. Issues and fixes faced during previous projects.
  • Q2. Placement, CTS, CMOS concepts
  • Q3. LVS, Design for manufacturing.

Skills evaluated in this interview

Interview experience
1
Bad
Difficulty level
Hard
Process Duration
2-4 weeks
Result
Not Selected

I applied via Recruitment Consulltant and was interviewed before Nov 2023. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Explain CGC cell working with circuit and waveforms
  • Ans. 

    CGC cell is a standard cell used in physical design with specific characteristics for circuit implementation.

    • CGC cell stands for Custom Gate Cell, which is a standard cell used in physical design for implementing logic functions.

    • CGC cells have specific characteristics like fixed height and width, predefined power and ground connections, and a set of pins for input and output signals.

    • When designing a circuit using CGC c...

  • Answered by AI
  • Q2. Draw tie cell diagram for both low/high cells
  • Ans. 

    Tie cell diagram for low/high cells in physical design engineering.

    • Tie cell diagram is used in physical design to connect multiple power domains.

    • Low tie cells are used to connect low power domains, while high tie cells are used for high power domains.

    • Examples of tie cells include power switches and isolation cells.

  • Answered by AI
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Naukri.com and was interviewed before May 2023. There were 2 interview rounds.

Round 1 - Technical 

(1 Question)

  • Q1. Which is the best sorting algorithm
  • Ans. 

    There is no one-size-fits-all answer as the best sorting algorithm depends on the specific use case and constraints.

    • The best sorting algorithm depends on factors such as the size of the data set, the range of values, whether the data is mostly already sorted or not, and the available memory.

    • For small data sets or nearly sorted data, insertion sort or bubble sort may be efficient.

    • For large data sets, quicksort, mergesor...

  • Answered by AI
Round 2 - Coding Test 

Write a program to print the permutations of abc

Skills evaluated in this interview

Interview Questionnaire 

1 Question

  • Q1. Line drawing algorithm , clone linked list
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via LinkedIn and was interviewed in May 2024. There was 1 interview round.

Round 1 - Coding Test 

Code for constraints
Code for driver

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Referral and was interviewed before Feb 2023. There was 1 interview round.

Round 1 - One-on-one 

(1 Question)

  • Q1. Merge two sorted linked lists without using extra space
  • Ans. 

    Merge two sorted linked lists without using extra space

    • Use a dummy node to start the merged list

    • Compare the values of the nodes in both lists and link the smaller one to the merged list

    • Move the pointer of the merged list and the pointer of the smaller node to the next node

  • Answered by AI

Skills evaluated in this interview

Interview experience
3
Average
Difficulty level
Hard
Process Duration
Less than 2 weeks
Result
No response

I applied via Walk-in and was interviewed in May 2024. There was 1 interview round.

Round 1 - Aptitude Test 

Distance between two stations

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. Discussed about the previous projects which you have worked on
  • Q2. Basic concepts of SV and UVN

TSMC Interview FAQs

How many rounds are there in TSMC Physical Design Engineer interview?
TSMC interview process usually has 1 rounds. The most common rounds in the TSMC interview process are Technical.
What are the top questions asked in TSMC Physical Design Engineer interview?

Some of the top questions asked at the TSMC Physical Design Engineer interview -

  1. Draw a simple timing setup and solution if viola...read more
  2. How can you solve noise/crosst...read more

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TSMC Physical Design Engineer Interview Process

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TSMC Physical Design Engineer Salary
based on 4 salaries
₹40 L/yr - ₹55 L/yr
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