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Sujo Plast
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I applied via Referral and was interviewed in Sep 2021. There were 3 interview rounds.
I applied via Campus Placement and was interviewed before Dec 2015. There were 2 interview rounds.
I applied via Campus Placement and was interviewed in Dec 2016. There were 3 interview rounds.
I applied via Campus Placement and was interviewed in Dec 2016. There were 5 interview rounds.
I applied via Recruitment Consultant and was interviewed before May 2020. There were 3 interview rounds.
Clone a linked list with random pointers.
Create a new node for each node in the original list.
Store the mapping between the original and cloned nodes in a hash table.
Traverse the original list again and set the random pointers in the cloned list using the hash table.
Return the head of the cloned list.
I applied via Referral and was interviewed in Feb 2020. There were 6 interview rounds.
posted on 14 Jan 2022
I applied via Referral and was interviewed before Jan 2021. There were 3 interview rounds.
posted on 11 Jun 2022
PPAP documents are developed in the Production Part Approval Process (PPAP) face.
PPAP documents are developed during the production part approval process.
This is typically the fourth phase of the APQP (Advanced Product Quality Planning) process.
PPAP documents include items such as control plans, FMEAs, and measurement system analysis.
The purpose of PPAP is to ensure that all parts meet customer requirements and specifi...
The shrinkage value of pa66 varies depending on the specific grade and processing conditions.
Shrinkage is the reduction in size of a molded part as it cools and solidifies.
The shrinkage value of pa66 can range from 1.5% to 3.5%.
Factors that affect shrinkage include mold design, processing parameters, and part geometry.
It is important to account for shrinkage when designing molds and parts to ensure proper fit and funct
I applied via Campus Placement and was interviewed before Oct 2022. There were 3 interview rounds.
UVM is a methodology for verifying complex designs using SystemVerilog. Blocking assignments execute sequentially, while non-blocking assignments execute concurrently.
UVM (Universal Verification Methodology) is a standardized methodology for verifying complex designs in SystemVerilog.
Blocking assignments in SystemVerilog execute sequentially, meaning the next statement waits for the current statement to finish.
Non-bloc...
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