Scaledge Interview Questions and Answers

Fundamental knowledge of aptitude, MPMC, C/C++, basic electronics, and digital electronics.

Q1. Mostly asked digital electronics and verilog, any programming language
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Q1. In depth questions from verilog and digital electronics
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Q1. About company policy family background etc
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Q1. What is Polymorphism in sv
Ans. 
Polymorphism in SystemVerilog allows objects of different types to be treated as objects of a common base type.
• Polymorphism allows for more flexibility and reusability in code

• It enables the use of virtual methods to be overridden in derived classes

• Example: Using a base class to define common methods and then creating derived classes that implement those methods differently
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Q2. What is Inheritance in sv
Ans. 
Inheritance in SystemVerilog allows a class to inherit properties and methods from another class.
• Inheritance allows for code reusability and promotes a hierarchical structure.

• Derived class inherits properties and methods from the base class.

• Derived class can also have its own unique properties and methods.

• Example: class B extends class A, where B inherits properties and methods from A.
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Normal genral aptitude questions are there
1.speed and time
2.permutation combination
3.percentage
4.profit loss
etc

Q1. Design a Xor gate using 4:1 mux?
Ans. 
Xor gate can be designed using 4:1 mux by selecting inputs based on control signals.
• Use 4:1 mux with two inputs as A and B, one input as A' and one input as B'.

• Connect A and B to select lines of mux.

• Connect A' and B' to the data inputs of mux.

• Set control signals such that when A=0, B=1 or A=1, B=0, the output is 1.

• When A=B=0 or A=B=1, the output should be 0.
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Q2. How to design full adder using half adder?
Ans. 
A full adder can be designed using two half adders and an OR gate.
• Use one half adder to add two of the three inputs (A and B)

• Use the second half adder to add the output of the first half adder with the third input (Cin)

• Use an OR gate to combine the carry outputs of both half adders to get the final carry out

• The sum output is the XOR of the outputs of both half adders
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Q1. Tell me about yourself?
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I am a passionate and experienced Design Engineer with a strong background in mechanical engineering and a proven track record of delivering innovative solutions.
• I have a Bachelor's degree in Mechanical Engineering from XYZ University.

• I have worked for XYZ Company for 5 years, where I led a team in designing a new product that increased efficiency by 20%.

• I am proficient in CAD software such as SolidWorks and AutoCAD.

• I ...read more
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Q2. What are your hobbies?
Ans. 
My hobbies include woodworking, hiking, and playing the guitar.
• Woodworking: I enjoy creating furniture and small projects in my spare time.

• Hiking: I love exploring nature trails and challenging myself with new hikes.

• Playing the guitar: I find relaxation and creativity in playing music on my guitar.
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Q1. Basic Verilog questions, Basic Digital Questions, if you know computer Architecture then few questions form pipeline,hazards,caches, lastly basic C questions
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Q2. Difference between task and function ?
Ans. 
Tasks are concurrent blocks of code that can run in parallel, while functions are sequential blocks of code that perform a specific task.
• Tasks can run concurrently, while functions run sequentially

• Tasks can be executed in parallel, while functions are executed one after the other

• Tasks are used for parallel processing, while functions are used for sequential processing
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Q3. Difference between blocking and non-blocking
Ans. 
Blocking operations wait until the operation completes, while non-blocking operations do not wait and allow other operations to continue.
• Blocking operations halt the execution until the operation is completed

• Non-blocking operations do not halt the execution and allow other operations to continue

• Blocking operations are synchronous, while non-blocking operations are asynchronous

• Example: In a blocking operation, a functio...read more
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Q4. Write an fsm code for patten detector
Ans. 
FSM code for pattern detector
• Define states for different patterns to detect

• Transition between states based on input pattern

• Output a signal when a specific pattern is detected
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Q1. Same as first interview
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