Filter interviews by
I applied via Walk-in and was interviewed before Feb 2023. There was 1 interview round.
I applied via Campus Placement and was interviewed before Oct 2022. There were 3 interview rounds.
UVM is a methodology for verifying complex designs using SystemVerilog. Blocking assignments execute sequentially, while non-blocking assignments execute concurrently.
UVM (Universal Verification Methodology) is a standardized methodology for verifying complex designs in SystemVerilog.
Blocking assignments in SystemVerilog execute sequentially, meaning the next statement waits for the current statement to finish.
Non-bloc...
posted on 15 Sep 2022
posted on 18 Jul 2022
I applied via Walk-in and was interviewed in Jun 2022. There was 1 interview round.
posted on 17 Mar 2025
I appeared for an interview before Mar 2024, where I was asked the following questions.
posted on 3 Apr 2021
I applied via Referral and was interviewed in Nov 2020. There were 3 interview rounds.
based on 1 interview
Interview experience
Account Assistant
5
salaries
| ₹2.3 L/yr - ₹3 L/yr |
Accountant
4
salaries
| ₹2.2 L/yr - ₹3 L/yr |
Architect
4
salaries
| ₹1 L/yr - ₹4.8 L/yr |
Retail Store Manager
4
salaries
| ₹2.2 L/yr - ₹2.4 L/yr |
Site Engineer
4
salaries
| ₹3 L/yr - ₹3.6 L/yr |
Primus Global Technologies
Practo
Magneti Marelli Motherson Auto System
TriGeo Technologies