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I applied via Approached by Company and was interviewed before Mar 2023. There was 1 interview round.
Python and java related question
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1hr interview, asked checker code, checked protocol knowledge mentioned in Resume, asked assertion.
posted on 5 Sep 2024
Dealing with a project deadline delay due to unexpected technical challenges
Identified root cause of the technical challenges
Collaborated with team members to brainstorm solutions
Adjusted project timeline and communicated with stakeholders
Worked extra hours to meet the revised deadline
Online test core topics like vlsi,digital design etc
I applied via campus placement at Indian Institute of Technology (IIT), Kanpur and was interviewed in Nov 2023. There was 1 interview round.
I applied via Referral and was interviewed in Aug 2023. There were 2 interview rounds.
Work and time, boat and stream question. basic digital questions, computer architecture
SRAM and DRAM are types of computer memory with different characteristics. Blocking and non-blocking statements are used in hardware design.
SRAM (Static Random Access Memory) is faster, more expensive, and consumes more power than DRAM (Dynamic Random Access Memory).
SRAM stores data in a flip-flop circuit, while DRAM stores data in a capacitor.
SRAM does not need to be refreshed, while DRAM requires periodic refreshing.
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1hr interview, asked checker code, checked protocol knowledge mentioned in Resume, asked assertion.
Online test core topics like vlsi,digital design etc
I applied via campus placement at Indian Institute of Technology (IIT), Kanpur and was interviewed in Nov 2023. There was 1 interview round.
I applied via Recruitment Consulltant and was interviewed before Nov 2023. There was 1 interview round.
CGC cell is a standard cell used in physical design with specific characteristics for circuit implementation.
CGC cell stands for Custom Gate Cell, which is a standard cell used in physical design for implementing logic functions.
CGC cells have specific characteristics like fixed height and width, predefined power and ground connections, and a set of pins for input and output signals.
When designing a circuit using CGC c...
Tie cell diagram for low/high cells in physical design engineering.
Tie cell diagram is used in physical design to connect multiple power domains.
Low tie cells are used to connect low power domains, while high tie cells are used for high power domains.
Examples of tie cells include power switches and isolation cells.
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