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Ribbon Communication Verification Engineer Interview Questions and Answers

Updated 3 Mar 2024

Ribbon Communication Verification Engineer Interview Experiences

1 interview found

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Approached by Company and was interviewed before Mar 2023. There was 1 interview round.

Round 1 - Coding Test 

Python and java related question

Interview Preparation Tips

Interview preparation tips for other job seekers - Overall good expierence

Interview questions from similar companies

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(4 Questions)

  • Q1. Asked about the details of my projects
  • Q2. Digital question related to flip flop and mux.
  • Q3. Assertion, constraint questions
  • Q4. Asked about different ways of saving power
Round 2 - Coding Test 

1hr interview, asked checker code, checked protocol knowledge mentioned in Resume, asked assertion.

Round 3 - One-on-one 

(4 Questions)

  • Q1. Draw Digital circuit question based on the waveform
  • Q2. Asked about code coverage in details
  • Q3. 1 technical puzzle, to print infinite series of a given pattern
  • Q4. 1 logical puzzle, 50ball in box of 1 colour and 50ball of 2nd colour in another box, calculate highest probability to choose 1 colour ball.

Interview Preparation Tips

Interview preparation tips for other job seekers - Be confident, Be throwly prepared
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - HR 

(1 Question)

  • Q1. Toughest time and how you handled
  • Ans. 

    Dealing with a project deadline delay due to unexpected technical challenges

    • Identified root cause of the technical challenges

    • Collaborated with team members to brainstorm solutions

    • Adjusted project timeline and communicated with stakeholders

    • Worked extra hours to meet the revised deadline

  • Answered by AI
Interview experience
1
Bad
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Aptitude Test 

Online test core topics like vlsi,digital design etc

Round 2 - Technical 

(3 Questions)

  • Q1. Few digital electronics questions one puzzle one vlsi question
  • Q2. Puzzle based on matricess
  • Q3. Vlsi question based on stacks
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via campus placement at Indian Institute of Technology (IIT), Kanpur and was interviewed in Nov 2023. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Going through resume and asking core related projects
  • Q2. And 2 maths related questions from sets and logical queston
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Not Selected

I applied via Referral and was interviewed in Aug 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

Work and time, boat and stream question. basic digital questions, computer architecture

Round 2 - Technical 

(1 Question)

  • Q1. Difference between SRAM and DRAM, bloacking and non blocking statement
  • Ans. 

    SRAM and DRAM are types of computer memory with different characteristics. Blocking and non-blocking statements are used in hardware design.

    • SRAM (Static Random Access Memory) is faster, more expensive, and consumes more power than DRAM (Dynamic Random Access Memory).

    • SRAM stores data in a flip-flop circuit, while DRAM stores data in a capacitor.

    • SRAM does not need to be refreshed, while DRAM requires periodic refreshing.

    • ...

  • Answered by AI

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(4 Questions)

  • Q1. Asked about the details of my projects
  • Q2. Digital question related to flip flop and mux.
  • Q3. Assertion, constraint questions
  • Q4. Asked about different ways of saving power
Round 2 - Coding Test 

1hr interview, asked checker code, checked protocol knowledge mentioned in Resume, asked assertion.

Round 3 - One-on-one 

(4 Questions)

  • Q1. Draw Digital circuit question based on the waveform
  • Q2. Asked about code coverage in details
  • Q3. 1 technical puzzle, to print infinite series of a given pattern
  • Q4. 1 logical puzzle, 50ball in box of 1 colour and 50ball of 2nd colour in another box, calculate highest probability to choose 1 colour ball.

Interview Preparation Tips

Interview preparation tips for other job seekers - Be confident, Be throwly prepared
Interview experience
1
Bad
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Aptitude Test 

Online test core topics like vlsi,digital design etc

Round 2 - Technical 

(3 Questions)

  • Q1. Few digital electronics questions one puzzle one vlsi question
  • Q2. Puzzle based on matricess
  • Q3. Vlsi question based on stacks
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via campus placement at Indian Institute of Technology (IIT), Kanpur and was interviewed in Nov 2023. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Going through resume and asking core related projects
  • Q2. And 2 maths related questions from sets and logical queston
Interview experience
1
Bad
Difficulty level
Hard
Process Duration
2-4 weeks
Result
Not Selected

I applied via Recruitment Consulltant and was interviewed before Nov 2023. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Explain CGC cell working with circuit and waveforms
  • Ans. 

    CGC cell is a standard cell used in physical design with specific characteristics for circuit implementation.

    • CGC cell stands for Custom Gate Cell, which is a standard cell used in physical design for implementing logic functions.

    • CGC cells have specific characteristics like fixed height and width, predefined power and ground connections, and a set of pins for input and output signals.

    • When designing a circuit using CGC c...

  • Answered by AI
  • Q2. Draw tie cell diagram for both low/high cells
  • Ans. 

    Tie cell diagram for low/high cells in physical design engineering.

    • Tie cell diagram is used in physical design to connect multiple power domains.

    • Low tie cells are used to connect low power domains, while high tie cells are used for high power domains.

    • Examples of tie cells include power switches and isolation cells.

  • Answered by AI

Ribbon Communication Interview FAQs

How many rounds are there in Ribbon Communication Verification Engineer interview?
Ribbon Communication interview process usually has 1 rounds. The most common rounds in the Ribbon Communication interview process are Coding Test.
How to prepare for Ribbon Communication Verification Engineer interview?
Go through your CV in detail and study all the technologies mentioned in your CV. Prepare at least two technologies or languages in depth if you are appearing for a technical interview at Ribbon Communication. The most common topics and skills that interviewers at Ribbon Communication expect are Analytics, Optical Networking, Automation Framework, Automation Testing and DWDM.

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Ribbon Communication Verification Engineer Interview Process

based on 1 interview

Interview experience

4
  
Good
View more

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Ribbon Communication Verification Engineer Salary
based on 21 salaries
₹6.3 L/yr - ₹15.1 L/yr
5% more than the average Verification Engineer Salary in India
View more details

Ribbon Communication Verification Engineer Reviews and Ratings

based on 5 reviews

2.8/5

Rating in categories

2.6

Skill development

1.9

Work-life balance

1.9

Salary

1.8

Job security

2.6

Company culture

2.0

Promotions

1.9

Work satisfaction

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