MediaTek India Technology Vlsi Hardware Interview Questions and Answers

It consisted of aptitude questions, then OS C 1mrks, which were re GATE questions. No coding, I chose hardware role, so questions were from digital electronics too. prepare the gate questions for these subjects

Q1. Question were from vlsi and SOC design
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Q2. Then questions on optimizations in vlsi were asked.
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Q1. Family and background check
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Q2. Resume and projects
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Basic ece ques and apti

Q1. What are flip flops and latches
Ans. 
Flip flops and latches are sequential logic circuits used in digital electronics to store and transfer data.
• Flip flops are clocked circuits that store one bit of data, while latches are level-sensitive circuits that store data as long as the enable signal is active.

• Flip flops are edge-triggered, meaning they change state on a clock edge, while latches are level-triggered, changing state as long as the enable signal is ...read more
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Q2. Verilog projects
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Aptitude, Digital Electronics.

Questions on dgital electronics and circuits

Q1. Questions on digital electronics , STA and FSM and Verilog
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Basic apptitude and digital and analog mcqs

Q1. Design a 3 input xor gate using 4:1mux
Ans. 
Use a 4:1 mux to create a 3 input XOR gate.
• Connect two of the inputs to the select lines of the mux.

• Connect the third input to one of the data inputs of the mux.

• Connect the other data input of the mux to the output of an XOR gate between the first two inputs.

• Use the output of the mux as the output of the 3 input XOR gate.
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Q1. Wasn't selected to hr round
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Q1. What is setup time ?
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Setup time is the amount of time a data input signal must be stable before the clock edge for proper operation of a flip-flop.
• Setup time is the minimum time required for the input data signal to be stable before the clock edge.

• It ensures that the data input is captured correctly by the flip-flop.

• If the setup time is not met, the flip-flop may capture the wrong data.

• Setup time violations can lead to timing issues in dig...read more
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Q2. 3 input xor and xnor gate
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