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I applied via Company Website and was interviewed in Feb 2024. There was 1 interview round.
Left shift 1011, xor connected to first and last bit, clk 1111 will be there when 1011 is shifted left.
Perform left shift operation on 1011: 1011 << 1 = 0110
XOR the first and last bit of the result: 0 XOR 0 = 0
The clock signal 1111 will be present when the result of the XOR operation is 0
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posted on 9 Mar 2024
I applied via campus placement at Vellore Institute of Technology (VIT) and was interviewed in Feb 2024. There was 1 interview round.
posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
posted on 7 May 2024
I applied via Referral and was interviewed in Apr 2024. There was 1 interview round.
Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.
Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.
Writing directed tests to cover specific state transitions can help achieve higher coverage.
Random stimulus generation can also be used to explore different state transitions.
Functional coverage can...
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
posted on 5 Apr 2024
posted on 29 Apr 2024
I applied via campus placement at Indian Institute of Technology (IIT), Kharagpur and was interviewed before Apr 2023. There were 2 interview rounds.
I plan to continue advancing my skills in design verification engineering and eventually move into a leadership role.
Continue taking relevant courses and certifications to stay updated on industry trends
Seek opportunities to lead projects and teams to gain leadership experience
Network with professionals in the field to learn from their experiences and insights
posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
posted on 27 Sep 2022
I applied via Company Website and was interviewed in Mar 2022. There were 3 interview rounds.
Had basic aptitude questions, verilog , c programming, digital electronics, analog electronics,computer architecture.
posted on 20 Jun 2024
I was interviewed before Jun 2023.
Tasks and functions refer to the specific responsibilities and roles assigned to an individual within a job or project.
Tasks are specific actions or activities that need to be completed within a certain timeframe.
Functions are broader roles or responsibilities that encompass multiple tasks and contribute to the overall goal.
Examples of tasks include writing test cases, debugging code, and creating design specifications...
Blocking assignments wait for the assigned value to be calculated before moving on to the next statement, while non-blocking assignments allow multiple assignments to occur simultaneously.
Blocking assignments use the = operator, while non-blocking assignments use the <= operator
Blocking assignments are executed sequentially in the order they appear in the code, while non-blocking assignments are executed concurrently
Bl...
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