Upload Button Icon Add office photos
filter salariesFilter salaries by

ProcSys FPGA and RTL Design Engineer salaries in India

Annual salary range
1 - 2 years exp.
₹6.3 Lakhs - ₹8 Lakhs
Low Confidence
info icon
Low confidence means that this average salary is based on data that was reported by very few people.
Salary of majority employees
unlock blur
unlock blur

Interested in this particular role?

Last Updated: 13 Sep 2024

Companies similar to ProcSys for FPGA and RTL Design Engineer

Company name Avg Annual Salary Open Jobs
Logo
HCLTech FPGA and RTL Design Engineer Salary

2 - 8 years exp. (4 salaries)

unlock blur

₹6 L/yr - ₹20.1 L/yr

arrow icon 62% more
Logo
Qualcomm FPGA and RTL Design Engineer Salary

1 - 6 years exp. (3 salaries)

unlock blur

₹6 L/yr - ₹19.2 L/yr

arrow icon 58% more
Logo
Intel FPGA and RTL Design Engineer Salary

3 - 8 years exp. (10 salaries)

unlock blur

₹15 L/yr - ₹45 L/yr

arrow icon 255% more
Logo
Amdocs FPGA and RTL Design Engineer Salary

3 - 5 years exp. (9 salaries)

unlock blur

₹19.4 L/yr - ₹40.5 L/yr

arrow icon 345% more
unlock blur

₹3.3 L/yr - ₹9 L/yr

arrow icon 26% less
FPGA and RTL Design Engineer salary at ProcSys ranges between ₹6.3 Lakhs to ₹8 Lakhs per year for employees with experience between 1 year to 2 years. Salary estimates are based on 2 latest salaries received from various employees of ProcSys.

Similar Designation salaries in ProcSys

unlock blur
₹5 L/yr - ₹6 L/yr
Senior Software Engineer Salary
(AmbitionBox Estimate)
unlock blur
₹7.3 L/yr - ₹9.3 L/yr

ProcSys FPGA and RTL Design Engineer Salary FAQs

What is the notice period for FPGA and RTL Design Engineer at ProcSys?
According to AmbitionBox, 100% of the ProcSys FPGA and RTL Design Engineers reported a notice period of 15 days or less.This is based on 2 responses on AmbitionBox in last 2 years.

Tell us how to improve this page.

ProcSys FPGA and RTL Design Engineer salary in India ranges between ₹6.3 Lakhs to ₹8 Lakhs. This is an estimate based on latest salaries received from employees of ProcSys.