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Atria Logic Design & Verification Engineer salaries in Vijayawada

Annual salary range
1 - 3 years exp.
₹5.5 Lakhs - ₹7.1 Lakhs
Low Confidence
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Low confidence means that this average salary is based on data that was reported by very few people.
Salary of majority employees
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Last Updated: 9 Jan 2025

Design & Verification Engineer salary at Atria Logic ranges between ₹5.5 Lakhs to ₹7.1 Lakhs per year for employees with experience between 1 year to 3 years. Salary estimates are based on 2 latest salaries received from various employees of Atria Logic.

Similar Designation salaries in Atria Logic

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₹3 L/yr - ₹5 L/yr

Top skills at Atria Logic for Design & Verification Engineer

System Verilog Debugging Perl FPGA VHDL Visual Basic Ethernet Test Cases System Verilog Ethernet Python Digital Design Perl FPGA Python

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Atria Logic Design & Verification Engineer Salary FAQs

What is the notice period for Design & Verification Engineer at Atria Logic in Vijayawada?
According to AmbitionBox, 50% of the Atria Logic Design & Verification Engineers in Vijayawada reported a notice period of 15 days or less, 50% reported a notice period of 3 Months.This is based on 2 responses on AmbitionBox in last 2 years.

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Atria Logic Design & Verification Engineer salary in Vijayawada ranges between ₹5.5 Lakhs to ₹7.1 Lakhs. This is an estimate based on latest salaries received from employees of Atria Logic.