Senior ASIC RTL SOC Design Lead

We are Hiring Senior ASIC/SoC RTL Leads/Managers with ~5-20 years of experience to join our Wipro team!

About the Role:

Expertise in SoC subsystem/IP design

Expertise in IP design, Subsystem/ Cluster and SoC level integration using Verilog/System Verilog

In depth knowledge on RTL quality checks (Lint, CDC)

Knowledge of synthesis and low power is a plus

Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

Good understanding of timing concepts

Knowledge of one or more of the interface protocols:

• PCIe
• DDR
• Ethernet
• I2C, UART, SPI

Expertise in setting up and using tools like

• Spyglass Lint/CDC
• Synopsys DC
• Verdi/Xcellium

Understanding of scripting languages like Make flow, Perl ,shell, python etc

Understanding of processor architecture and/or ARM debug architecture is a plus

Able to help and debug issues for multiple subsystems

Able to create/review design documents for multiple subsystems

Able to support physical design, verification, DFT and SW teams on design queries and reviews.