Memory Layout Design Engineer - Cadence Virtuoso (4-8 yrs)

Experience : 4 - 8 Years

Job Description :

We are seeking a highly skilled and motivated Memory Layout Design Engineer to join our offshore development teams . The ideal candidate will have expertise in advanced process nodes (TSMC 3nm & 5nm) and a strong background in layout design for memory technologies. This role involves working on cutting-edge designs for high-performance and low-power applications, contributing to the development of next-generation semiconductor solutions

Role & responsibilities :

1. Layout Design and Verification :

- Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler.

- Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules.

2. Collaboration with Design Teams :

- Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA).

- Provide feedback on circuit designs to improve layout efficiency.

3. Process Technology Expertise :

- Understand and implement layout requirements for advanced nodes (3nm, 5nm, 7nm), including FinFET architecture and challenges such as variability and manufacturability.

- Address process-dependent effects like electromigration (EM), IR drop, and self-heating.

4. Tool Proficiency :

- Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits).

- Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL).

5. Quality and Optimization :

- Optimize layouts for yield enhancement and manufacturing robustness.

- Perform debugging of silicon failures and identify layout-related issues.

NOTE : Preferred resources holding valid regional work permits only