Verification Engineer

Roles and Responsibilities

• Design verification using System Verilog, UVM, OVM, C/C++.
  
• Experience with IP/Subsystem Verification on SOCs (preferably).
  
• Strong understanding of protocols such as Ethernet, SATA/SAS, USB, PCIe, CXL.
  
• Knowledge of testbench development and simulation tools like NCSIM/VCS.
  
• Familiarity with formal verification techniques an added advantage.