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111 UST Jobs
Emulation Verification Engineer
UST
·
4-9 years
₹ 15 - 25L/yr
Chennai, Coimbatore, Malaysia
15 vacancies
Emulation Verification Engineer
UST
posted 5d ago
Job Description
Emulation Verification Engineer
Job Description:
- Involve Emulation based functional verification that includes test plan definition, test content development.
- Good understanding in Verilog, emulation model compilation, waveform debugs.
- Experience with scripting programs like Python, TCL
- Basic understanding in AXI. Knowledge in PCIE is a plus.
- Basic understanding in System Verilog
Employment Type: Full Time, Permanent
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What people at UST are saying
Rating based on 2 Verification Engineer
reviews
Anonymous · Engineering - Hardware & Networks
in Bangalore / Bengaluru
Good office Good culture
No dislike Appraisal can be improved
- Salary - Poor
Verification Engineer salary at UST
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Emulation Verification Engineer
4-9 Yrs
₹ 15 - 25L/yr
Chennai, Coimbatore, Malaysia
Software Engineer (SAS/Python & Statistical Modeling)
5-10 Yrs
Mumbai, Gurgaon / Gurugram, Chennai
