Analog Mixed Signal Verification Engineer

Verification of Mixed-Signal designs at chip and module level.

Analog/Mixed-Signal self-checking simulation.

Implementation of analog models in Verilog-/VHDL-AMS to speed up AMS simulation.

Application of metric-driven Verification (MDV) methodologies.

Development and tracking of Verification plans.

Integration of Verification-IP.

Measurement and analysis of regression results.

Cooperate on evaluation of silicon, test correlation, and scripting (Perl, Python, C++).

Work with verification team on verification plans, test cases, and analyzing test results.

Very good experience in Verilog AMS , Verilog-A, WREAL, modelling of analog blocks.

Very good experience in analog mixed signal simulation tools.

Good experience in System Verilog, UVM methodologies.

Good experience in creating AMS Verification environment and able to create AMS Verification environment from scratch.

Good experience in Gate level netlist simulation.

Experience in Python, Perl, Shell scripting is desirable.Role & responsibilities