Analog Design, Sr Staff Engineer

We are hiring highly competent technical experts for our next generation memory interface PHY IPs (DDR/HBM/UCIe).

Responsibilities:

• Lead next generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) development
• Drive innovation towards high-speed IO designs for memory interface PHY IP in CMOS/FinFET/GAA
• Collaborate with cross-functional teams across globe

• Qualification: BTech/MTech
• Proficient in analog design fundamentals, device physics
• Expert in high-speed IO designs in advanced technologies
• Knowledge of JEDEC requirements for memory interfaces and standards would be a plus
• Good understanding of ESD and reliability concepts
• Familiarity with signal integrity and/or power integrity is a plus
• Drive design teams to deliver best quality products
• Excellent written, verbal communication and interpersonal skills