R&D Engineering, Sr Engineer

• A person in the position would be responsible for designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for technology mapping, logic and timing optimization steps of the FPGA logic synthesis software.

The person is expected to

• Given a requirement or functional specification, design and implement efficient data structures and algorithms in C/C++.
• Work with CAE team in test planning, execution and customer support. o Maintain and support existing product and features.

Expected background and skill

• B. Tech/M. Tech in CS/EE from a reputed institute.
• 2+ years of experience in designing, developing and maintaining large EDA software.
• Sound knowledge in data structures, graph algorithms and C/C++ programming on Windows/Unix.
• Familiarity in digital logic design.
• Familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis.
• Working knowledge of FPGA design tools and flows is a plus.