Senior ASIC/RTL Design Engineer (7-8 yrs)

Role : ASIC RTL Design Engineer.

Location : Noida.

Notice Period : Immediate to 15days.

Key Responsibilities :

- Develop and maintain high-quality RTL code for ASIC IPs and SoCs using Verilog

- Possess a deep understanding of digital design concepts and translate them into efficient RTL constructs

- Design and integrate complex IP blocks with a focus on performance, power, and area optimization

- Utilize Synopsys/Cadence/Mentor simulation tools for functional verification and debugging

- Experience with RTL logic synthesis, SDC writing, and constraint management is a plus

- Possess a strong understanding of basic SoC architecture, including standard cells and I/O blocks

- Collaborate effectively with cross-functional teams to ensure project success

Requirements :

- 7+ years of experience in ASIC design with a strong focus on RTL development

- Expertise in Verilog/RTL coding for IP and SoC design In-depth knowledge of digital logic design principles and methodologies

- Proven experience in designing and integrating large-scale IP blocks

- Proficiency in Synopsys/Cadence/Mentor simulation tools for functional verification and debugging

- Familiarity with Perl/TCL scripting for automation (desirable)

- Prior experience with RTL logic synthesis, SDC writing, and constraint management (desirable)