ASIC Physical Design, Sr Engineer

Should be strong in technical concepts, fundamentals, and good team player. The role involves daily technical interaction with local, US counter parts. He/She will be part of SNPS DDR IP implementation team and responsible for the implementation and integration of world class DDR IPs at the cutting edge technology nodes (3nm,5nm,7nm,10nm and below). Timing closure above ~4GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR timing closure, implementation would be an added advantage.