Senior Design Engineer - Physical Design

• BE/BTech in Computer Science or Electronics or Electrical

• 5+ years of relevant experience

REQUIRED KNOWLEDGE, SKILLS, AND ABILITIES

• Work experience with node 5nm or lower node designs with advanced low power techniques is must.
• Experience on ASIC Physical Design: Floorplanning, P&R, extraction, IR Drop Analysis, Timing and
• Signal Integrity closure, Physical Verification are essential part of the job.
• Well versed with Cadence or Synopsys tools is important.
• Experience with Static Timing Analysis in Primetime or Primetime-SI is important.
• Hands-on experience in scripting languages such as PERL, TCL is important.
• Implement robust clock distribution solutions using appropriate methods that meet design
• requirements.
• Make good independent technical trade-offs between power, area, and timing (PPA).
• Interact with Design team to help drive and resolve design issues related to PnR closure.
• Timing closure on high-speed interfaces is a plus.
• Knowledge on Full chip Physical Design is beneficial.
• Good ASIC fundamentals and problem-solving skills is preferred.

MANDATORY SKILLS

• Experience with 5nm node.
• Experience with Cadence Innovus.