FPGA Design Engineer - VHDL (5-10 yrs)

Position Summary :

The ideal candidate will have an understanding of VHDL/Verilog, and expertise in DSP and communication protocols. This role involves developing and optimizing FPGA designs for DSP.

Key Responsibilities :

- Design and implement FPGA-based systems using Xilinx RFSoC, MPSoC, and related architectures.

- Use EDA tools like Xilinx Vivado, ModelSim, and MATLAB (DSP Blockset) for design, simulation, and debugging.

- Implement signal demodulation schemes such as BFM, FSK, BFSK, MSK, GFSK, GMSK, BPSK, QPSK, 8PSK, OQPSK, and QAM.

- Design and integrate decoding modules, including Bit De-Interleavers, HDB3 Decoders, and Forward Error Correction (FEC) algorithms such as Reed-Solomon.

- Develop solutions for de-scrambling, convolution decoding, and deframing for protocols like E1, E3, T1, and T3.

- Work with standards such as ATSC1, ATSC2, DVB-T/T2/H, and DTMB to deliver compliant FPGA designs.

Required Qualifications :

- Bachelor's or Master's degree in Electronics.

- Strong understanding of DSP, including RFSoC and MPSoC.

- Hands-on experience with EDA tools such as Xilinx Vivado, ModelSim, and MATLAB DSP Blockset.

- Expertise in signal demodulation schemes and communication protocols.

- In-depth knowledge of decoding techniques, FEC algorithms, and multimedia processing.

- Familiarity with digital broadcast standards such as ATSC, DVB, and DTMB.

- Experience in deframing (E1, E3, T1, T3) and handling MPEG video/audio data.

- Knowledge of RF design and testing for communication systems.